RejSCore: New Hardware Accelerator Boosts Post-Quantum Crypto Efficiency
Researchers have developed RejSCore, a hardware accelerator designed to efficiently perform rejection sampling in post-quantum cryptographic systems. The team, led by Patrick Karl, presented their work at the DATE 2021 conference in Grenoble, France.
RejSCore demonstrates substantial improvement in resource efficiency. It has been implemented on both Artix-7 FPGAs and 65nm CMOS technology, showing significant reductions in area and power consumption for schemes like QR-UOV without compromising performance.
On Artix-7 FPGAs, RejSCore operates at 222MHz with an area of 2042 slices. On 65nm CMOS, it operates at 565MHz with an area of 464,866 μm2. The accelerator completes its operation in 8525 clock cycles when processing QR-UOV parameters for security level I.
The team employed a lightweight iterative architecture for rejection sampling to minimize resource consumption. RejSCore is suitable for deployment in environments demanding both security and limited resources, such as embedded systems and edge devices. It incorporates an AES-CTR-128-based pseudorandom number generator for efficient random value generation.
RejSCore, developed by Patrick Karl and his team, offers a promising solution for efficient rejection sampling in post-quantum cryptographic systems. With its demonstrated resource efficiency and performance, it is well-suited for resource-constrained environments. The team plans to extend RejSCore's capabilities to encompass all security levels within the QR-UOV scheme in future work. More information about RejSCore can be found on ArXiv: https://arxiv.org/abs/2510.22661.
